Application-specific integrated circuits (ASICs) and other types of complex electronic circuits are often designed using Register Transfer Level (RTL) techniques. In an RTL-based design process, the design is initially expressed in a high level computer language such as VHSIC (very High Speed Integrated Circuit) Hardware Description language (VHDL), which is a standard of the Institute of Electrical and Electronics Engineers (IEEE). The design as expressed in the high level language is then converted to a gate-level description using a process referred to as synthesis. The synthesis process optimizes the gate-level description within the area and timing constraints of the particular design. The complexity of the synthesis process typically requires that a large ASIC design be partitioned into several modules which are then synthesized separately, often by different designers. Before entering the synthesis process, the modules are simulated in RTL VHDL format using functional vectors to verify the desired functionality of the module. This simulation is also performed on the complete set of RTL VHDL code for the design.
ASICs and other complex circuits may also make use of Design for Test (DFT) techniques which modify the design to ensure that the final gate-level design is testable for internal faults such as "stuck-at-one" or "stuck-at-zero" conditions on signal lines, A gate-level design is generally considered testable if it is possible to obtain a sufficiently high fault coverage by using test vectors generated by an automatic test pattern generator program or by on-chip logic configured to provide a function referred to as Built-In Self Test (BIST). BIST eliminates the need for test generation and allows at-speed testing by embedding test generation and signature computation hardware within the design. For example, a scan-based BIST technique involves connecting a series of flip-flops in the gate-level design into a scan chain. A control signal may then be set to a particular value in order to place the circuit into a scan mode, such that logic values can be shifted from one flip-flop to the next with every clock cycle, his allows testing of combinational logic between the flip-flops which would otherwise be very difficult to observe and control to a specific value during test.
Conventional scan chains for BIST are often constructed by modifying the flip-flops in the gate-level design. A scan chain implemented in this manner generally results in an extra multiplexor delay for signals passing through the corresponding flip-flops, as well as additional loading on the flip-flop outputs. In RTL-based design applications, this implementation of conventional scan chains can lead to new violations of the timing and area constraints, thus requiring that a computationally-intensive and costly re-optimization phase be performed on the entire design at the end of the design process. Implementing scan-based BIST using conventional techniques thus unduly increases the cost and complexity of the overall design process.
A number of approaches have attempted to implement DFT functions at the RTL VHDL level of a design. These approaches are described in, for example, S. Bhattacharya and S. Dey, "H-SCAN: A High Level Alternative to Full-Scan Testing with Reduced Area and Test Application Overheads," 14.sup.th VLSI Test Symposium, IEEE, pp. 74-80, 1996; R. S. Norwood and E. J. McCluskey, "Synthesis-for-Scan and Scan Chain Ordering," 14.sup.th VLSI Test Symposium, IEEE, pp. 87-92, 1996; K. D. Wagner and S. Dey, "High-Level Synthesis for Testability: A Survey and Perspective," Proceedings of Design Automation Conference, pp. 131-136, 1996; and C. Papachristou and J. Carletta, "Test Synthesis in the Behavioral Domain," Proceedings of the International Test Conference, IEEE, pp. 693-702, 1995, all of which are incorporated by reference herein. However, each of these approaches has one or more significant drawbacks. For example, some of these approaches fail to provide scan chains which can be used for applying diagnostic or supplementary deterministic vectors, while at least one other fails to provide scan-based BIST functions suitable for use in a wide variety of designs.